TSMC lays groundwork for Apple to design 5nm chips

“TSMC has announced delivery of the complete version of its 5nm design infrastructure within the Open Innovation Platform (OIP),” Jessie Shen reports for DigiTimes.
“TSMC’s 5nm process is already in risk production and offers IC designers a new level of performance and power optimization targeted at the next generation of high-end mobile and HPC applications. Compared with TSMC’s 7nm process, its innovative scaling features deliver 1.8X logic density and 15% speed gain on an ARM Cortex-A72 core, along with superior SRAM and analog area reduction enabled by the process architecture, TSMC said,” Shen reports. “The 5nm process enjoys the benefits of process simplification provided by EUV lithography, and is making excellent progress in yield learning, achieving the best technology maturity at the same corresponding stage as compared to TSMC’s previous nodes.”
Shen reports, “‘TSMC’s 5-nanometer technology offers our customers the industry’s most advanced logic process to address the exponentially growing demand for computing power driven by AI and 5G,’ said Cliff Hou, VP of R&D and technology development at TSMC. “5-nanometer technology requires deeper design-technology co-optimization. Therefore, we collaborate seamlessly with our ecosystem partners to ensure we deliver silicon-validated IP blocks and EDA tools ready for customer use. As always, we are committed to helping customers achieve first-time silicon success and faster time-to-market.'”
Read more in the full article here.
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